1. Field of the Invention
The present invention relates generally to internal memory systems, and more particularly, to a low-latency scratchpad RAM.
2. Discussion of the Related Art
Cache memory systems are well known and provide fast temporary data storage in a manner essentially transparent to the user. FIG. 1 illustrates a conventional memory architecture 100. Memory architecture includes microprocessor 110, which further includes cache controller 112 and primary cache 114. Primary cache 114 is an internal cache memory, typically with a size of 8 kilobytes-32 kilobytes. Primary cache 114 can be split into separate portions, one portion containing data (D-cache) and the other portion containing instructions (I-cache).
In a typical memory access, microprocessor 110, through on-chip cache controller 112, attempts to access the next instruction or data in primary cache 114. If the instruction or data is present in primary cache 114, a primary-cache hit occurs and microprocessor 110 retrieves the instruction or data from primary cache 114. If the instruction or data is not present in primary cache 114, a primary-cache miss occurs. Microprocessor 110 may then attempt to retrieve the instruction or data from an optional secondary cache 120. Secondary cache 120 is an external cache memory, typically with a size of 128 kilobytes to 4 Megabytes, that is accessed via bus interface unit (BIU) 116. If the instruction or data is not present in secondary cache 120 a secondary-cache miss occurs, at which time, microprocessor 110 would attempt to retrieve the instruction or data from further levels of cache or from main memory 130. As illustrated in FIG. 1, BIU 116 can also be configured to control the main memory bus interface.
In addition to the memory elements described above, it may also be desired to have a scratchpad RAM memory that can be reserved for direct and private usage by the microprocessor for tasks such as temporary storage or for communicating between processes. As the scratchpad RAM memory is a direct and private resource of the microprocessor, low latency in the access of the scratchpad RAM memory is desired.
The present invention addresses the aforementioned needs by providing a low-latency scratchpad RAM memory system that can be accessed in parallel to a primary cache. In accordance with the present invention, parallel access to the scratchpad RAM memory can be designed to be independent of a corresponding cache tag RAM. Accordingly, it is a feature of the present invention that the scratchpad RAM memory can be sized to any specification, independent of the size of the primary cache data RAMs.